1. Field of the Invention
The invention relates to a display panel driving apparatus for generating a drive pulse for driving a display panel having a capacitive load such as plasma display panel (hereinafter, referred to as “PDP”) or electroluminescence (hereinafter, referred to as “EL”).
2. Description of Related Art
Nowadays, display apparatus using a flat panel of a self light emitting type such as PDP or EL is put on the market as the so called wall-mounted TV.
FIG. 1 is a block diagram schematically showing the construction of the flat panel display apparatus.
In FIG. 1, a PDP 10 as a display panel has row electrodes Y1 to Yn and X1 to Xn constituting row electrode pairs in which one pair of X and Y corresponds to each row (the first row to the nth row) of one screen. Further, column electrodes Z1 to Zm corresponding to each column (the first column to the mth column) of one screen are formed on the PDP 10 so as to perpendicularly cross the row electrode pairs and sandwich a dielectric layer and a discharge space (not shown). One discharge cell C(i, j) is formed in a crossing portion of one row electrode pair (X, Y) and one column electrode Z.
First, a row electrode driving circuit 30 generates a reset pulse RPy of a positive voltage as shown in FIG. 2 and simultaneously applies it to each of the row electrodes Y1 to Yn. Simultaneously, a row electrode driving circuit 40 generates a reset pulse RPx of a negative voltage and simultaneously applies it to all of the row electrodes X1 to Xn.
By the simultaneous application of those reset pulses RPx and RPy, all discharge cells of the PDP 10 are discharge-excited and charged particles are generated. After the termination of the discharge, a predetermined amount of wall charges are uniformly formed in the dielectric layers of all of the discharge cells (resetting step).
After the completion of the resetting step, a column electrode driving circuit 20 generates pixel data pulses DP1 to DPn according to the pixel data corresponding to each of the first row to the nth row of the screen. Those pixel data pulses are sequentially applied to the column electrodes Z1 to Zm as shown in FIG. 2. The row electrode driving circuit 30 generates a scanning pulse SP of a negative voltage in accordance with the timing of application of each of the pixel data pulses DP1 to DPn and sequentially applies it to the row electrodes Y1 to Yn as shown in FIG. 2.
Among the discharge cells belonging to the row electrodes to which the scanning pulse SP has been applied, a discharge occurs in the discharge cells to which the pixel data pulse of the positive voltage has been further simultaneously applied, so that most of their wall charges are extinguished. On the other hand, no discharge occurs in the discharge cells to which the pixel data pulse of the positive voltage is not applied although the scanning pulse SP is applied. The wall charges remain in these discharge cells. In this way, the discharge cells whose wall charges remain become light emission discharge cells and the discharge cells whose wall charges have been extinguished become non-light emission discharge cells (addressing step).
After the completion of the addressing step, the row electrode driving circuit 30 continuously applies a sustain pulse IPy of a positive voltage to each of the row electrodes Y1 to Yn as shown in FIG. 2. At the same time, the row electrode driving circuit 40 continuously applies a sustain pulse IPx of a positive voltage to each of the row electrodes X1 to Xn at timing deviated from applying timing of the sustain pulse IPy. While the sustain pulses IPx and IPy are alternately applied, the light emission discharge cells whose wall charges remain repeat a discharge light emission and sustain a light emitting state (sustain discharging step).
A drive control circuit 50 shown in FIG. 1 generates various switching signals for generating various drive pulses as shown in FIG. 2 based on the timing of the video signal being supplied, and supplies them to each of the column electrode driving circuit 20 and the row electrode driving circuits 30 and 40. In other words, each of the column electrode driving circuit 20 and the row electrode driving circuits 30 and 40 generates the various drive pulses as shown in FIG. 2 in response to the switching signals which are supplied from the drive control circuit 50.
FIG. 3 is a diagram showing a drive pulse generating circuit which is provided in the row electrode driving circuit 30 and is operative to generate each of the reset pulse RPy and the sustain pulse IPy.
In FIG. 3, a capacitor C1 whose one end is connected to the ground, that is, a PDP earth potential Vs as the earthing potential of the PDP 10 is provided for the drive pulse generating circuit.
A switching device S01 is in a disconnecting state (OFF state) while a switching signal SW01 at the logic level “0” is supplied from the drive control circuit 50. The switching device S01 is in a connecting state (ON state) when the logic level of the switching signal SW01 is equal to “1” and applies an electric potential developed at the other end of the capacitor C1 onto a line 2 via an inductor L1 and a diode D1. The capacitor C1, therefore, starts to discharge and an electric potential developed by the discharge is applied onto the line 2.
A switching device S02 is in a disconnecting state (OFF state) while a switching signal SW02 at the logic level “0” is supplied from the drive control circuit 50. The switching device S02 is in a connecting state (ON state) when the logic level of the switching signal SW02 is equal to “1” and applies an electric potential on the line 2 to the other end of the capacitor C1 via an inductor L2 and a diode D2. That is, the capacitor C1 is charged by the electric potential on the line 2.
A switching device S03 is in a disconnecting state (OFF state) while a switching signal SW03 at the logic level “0” is supplied from the drive control circuit 50. The switching device S03 is in a connecting state (ON state) when the logic level of the switching signal SW03 is equal to “1” and applies an electric potential Vc at a positive side terminal of a DC power source B1 onto the line 2. The PDP earth potential Vs is applied to a negative side terminal of the DC power source 1.
A switching device S04 is in a disconnecting state (OFF state) while a switching signal SW04 at the logic level “0” is supplied from the drive control circuit 50. The switching device S04 is in a connecting state (ON state) when the logic level of the switching signal SW04 is equal to “1” and applies the PDP earth potential Vs onto the line 2.
The line 2 is connected to a row electrode Y of the PDP 10 having a capacitive component C0. Thus, in the row electrode driving circuit 30, the circuit shown in FIG. 3 is provided for each of n channels corresponding to the row electrodes Y1 to Yn.
FIG. 4 is a diagram showing the timing of each of the switching signals SW01 to SW04 which are supplied from the drive control circuit 50 to the row electrode driving circuit 30 shown in FIG. 3 in order to generate the sustain pulse IPy as shown in FIG. 2 on the line 2.
As shown in FIG. 4, first, the switching signal SW04 among the switching signals SW01 to SW04 is only at the logic level “1”, so the switching device S04 takes the ON state and the PDP earth potential Vs is applied on the line 2. Therefore, during this period of time, the electric potential on the line 2 is equal to the PDP earth potential Vs, that is, 0 [V].
Subsequently, when the switching signal SW04 is switched to the logic level “0” and the switching signal SW01 is switched to the logic level “1”, only the switching device S01 takes the ON state and the charges accumulated in the capacitor C1 are discharged. A current, therefore, flows transiently in the inductor L1 in a form as shown in FIG. 4. The current flows into the PDP 10 via the diode D1, switching device S01, and line 2 and the capacitive component C0 of the PDP 10 is charged, so that the electric potential on the line 2 rises gradually as shown in FIG. 4.
Subsequently, when the switching signal SW01 is switched to the logic level “0” and the switching signal SW03 is switched to the logic level “1”, only the switching device S03 takes the ON state and the electric potential Vc at the positive side terminal of the DC power source B1 is applied onto the line 2. During the period of time, therefore, the electric potential on the line 2 is fixed to Vc as shown in FIG. 4.
Subsequently, when the switching signal SW02 is switched to the logic level “1” and the switching signal SW03 is switched to the logic level “0”, only the switching device S02 takes the ON state and a negative current flows transiently in the inductor L2 in a form as shown in FIG. 4. That is, the capacitive component C0 of the PDP 10 which has been charged as mentioned above is discharged and the current flows into the capacitor C1 via the line 2, inductor L2, diode D2, and switching device S02 and is collected. The electric potential on the line 2, therefore, decreases gradually as shown in FIG. 4.
By the operation as mentioned above, the sustain pulse IPy of the positive voltage as shown in FIG. 4 is applied onto the line 2.
As for the voltage which is used when the capacitive load such as a PDP is driven, a relatively high voltage value in a range from tens of volts to a hundred and tens of volts is generally used. In the construction of the conventional driving circuit shown in FIG. 3, therefore, there is a problem that a resonance current flowing at the time of charging or discharging the capacitive load also increases and a large electric power loss occurs.
A withstanding voltage of each switching device included in the driving circuit of each of the row electrodes and the column electrodes is determined by the maximum value of a drive pulse voltage which is applied to each device. To assure a withstanding voltage enough for the high voltage mentioned above, therefore, it is necessary to use the switching device of a high withstanding voltage. Use of the switching device of the high withstanding voltage becomes an obstacle to the realization of low costs and miniaturization of the driving circuit.
FIGS. 5 and 6 show examples of a display panel driving circuit which is provided in the electrode driving circuit and generates various drive pulses such as reset pulse RPy and sustain pulse IPy. Those circuits generate the drive pulses by using the charge/discharge of the capacitor due to the resonance of an LC circuit comprising the inductor and the capacitor. That is, in consideration of a point that each discharge cell of the PDP 10 is a capacitive load, a resonance circuit is formed by combining the inductor as an inductive device and the capacitor for collecting an electric power to the discharge cell. The resonance circuit is excited at predetermined timing by using a switching device such as an FET, thereby generating a desired pulse.
The circuit of FIG. 5 has conventionally widely been used as a display panel driving circuit and is referred to as a “single-stage resonance circuit” hereinbelow for convenience of explanation. The circuit shown in FIG. 6 intends to reduce the withstanding voltage of the device used in the single-stage resonance circuit and is similarly referred to as a “double resonance circuit” below.
As for the voltage which is used when the capacitive load such as a PDP is driven by the resonance current, a relatively high voltage value in a range from tens of volts to a hundred and tens of volts is generally used. In the conventional display panel driving circuits shown in FIGS. 5 and 6, therefore, there is a problem such that a resonance current flowing at the time of charging or discharging the capacitive load also increases and a large electric power loss occurs when the load is driven.
Particularly, in the double resonance circuit shown in FIG. 6, although the withstanding voltage of the device used in the circuit is reduced more than that in the single-stage resonance circuit, there is a chance of occurrence of a problem as described below. That is, the double resonance circuit has a construction such that a potential transition circuit comprising the switching device, capacitor, and the like is added to the single-stage resonance circuit of FIG. 5 in order to raise the electric potential which is applied to the resonance circuit step by step. The resonance current, therefore, passes through a switching device SW11 or SW12 constituting the potential transition circuit and a surplus electric power loss due to an ON resistance of the device is caused. A parasitic capacitance Ck is caused between electric potential lines (OUTa and OUTb in FIG. 6) on the positive and negative sides of a pulse output and the ground or a power source. Since the parasitic capacitance Ck is excited by the power voltage V/2, there also is a chance that a power lossn×Ck×(V/2)2further occurs. In this expression, n indicates the number of repetition times in the unit time of the drive pulse.